1. Field of Invention
The present invention relates to a chipset and a related method, and more particularly to a chipset and a related method for controlling an external graphic module and an internal graphic module to transmit or receive signals simultaneously.
2. Related Art
For early computer system, chipset, for example, a north bridge (NB) device, is an important component for processing signals transmitted between central processing unit (CPU) and electronic devices such as memory, graphic card and peripheral device. Accompanying with the progressive multimedia technology, the interaction between a graphic memory device and a computer has been advanced. However, a computer not always equips an independent graphic card, in recent years a graphic chip is integrated in a computer chipset in some cases, for example, making a chipset have a graphic function by integrating a graphic chip in the chipset. Furthermore, chipset has an advancing integration, which means, it can integrate numbers of functions. Accordingly, a current chipset always equips an internal graphic module. However, a computer needs equip an external graphic card extra for getting advancing display function or more comprehensive graphic function.
Please refer to FIG. 1, a schematic diagram showing a conventional chipset. The chipset 1 includes an internal graphic module 11, a multiplexer 13 and a pad 15. Moreover, the chipset 1 is connected with an external graphic module 2, while the internal graphic module 11 is connected with the multiplexer 13 and transmits a 24 bit slow-voltage differential signal (LVDS) 111 to the multiplexer 13. The external graphic module 2 is a peripheral component interconnect express (PCIE) graphic engine, and transmits a PCIE signal 21 to the multiplexer 13, wherein the PCIE signal 21 is generally transmitted through 16 lanes (×16).
However, as show in FIG. 1, the multiplexer 13 cannot process the LVDS 111 and the PCIE signal 21 simultaneously. In other words, when the multiplexer 13 is processing the LVDS 111, the PCIE signal 21 from the external graphic module 2 cannot to be processed by the multiplexer 13 until the multiplexer 13 finishes the processing of the LVDS 111. On the contrary, when the multiplexer 13 is processing the PCIE signal 21, the LVDS 111 from the internal graphic module 11 cannot to be processed by the multiplexer 13 until the multiplexer 13 finishes the processing of the PCIE signal 21. As a result, the signals from the internal graphic module 11 and the external graphic module 2 cannot be processed simultaneously, thus the processing of the graphic signals is delay, and the processing speed slows down.
Therefore, for the improvement of the processing of the graphic signals, it has become an important issue to provide a chipset, a computer system and a related control method to resolve the aforementioned problem.